1. Field of the Invention
The present invention relates to a semiconductor device suitable for use in a battery-driven device such as a portable telephone, and more particularly to a semiconductor device which realizes reduced power consumption in a stand-by state.
2. Description of the Related Art
In general, a receiving circuit to which a power is supplied even in a stand-by state waiting for an external signal and an internal circuit to which no power is supplied in the stand-by state are incorporated into a battery-driven device such as a portable telephone and a notebook-sized personal computer. A plurality of complementary MOS (CMOS) transistors are incorporated into the receiving circuit and the internal circuit, and these transistors are fabricated by substantially the same fabrication process. Therefore, the thickness of gate oxide films of N-channel MOS transistors and P-channel MOS transistors respectively forming these CMOS transistors are substantially the same. In general, the thickness of the gate oxide film is about 50xc3x85. Low power consumption is desired for the receiving circuit, and a high-speed operation is desired for the internal circuit. Therefore, the threshold value of the CMOS transistor in the receiving circuit is set to be higher than that in the internal circuit. Such an adjustment of the threshold value is done by adjusting the conditions for implanting channel ions into a well.
In recent years, the operating voltage of the entire device has been reduced in order to reduce power consumption, changing from 5 V to 3.2 V and then to 1 V. However, if the operating voltage of the device is simply reduced, the operation speed thereof is also reduced. Therefore, by reducing the threshold value and the thickness of the gate oxide film, the operation speed is maintained.
However, there is a limit in reducing the threshold value. Although an adjustment for maintaining the operation speed is mainly performed by reducing the thickness of the gate oxide film, a reduction in the thickness of the gate oxide film results in a great increase in a gate leakage current. Since the gate leakage current flows from a gate to a substrate even in the stand-by state, power consumption of the receiving circuit in the stand-by state is increased.
FIG. 1 is a graph showing the relations between a gate voltage and a gate leakage current in various gate oxide film thicknesses. The horizontal axis of the graph shows a gate voltage, and the vertical axis thereof shows a gate leakage current. As shown in FIG. 1, as the gate voltage is increased or the gate oxide film thickness is reduced, the gate leakage current is increased. Accordingly, the gate leakage current greatly depends on the thickness of the gate oxide film. For example, as shown in FIG. 1, if the thickness of the gate oxide film is reduced by 4 xc3x85, the gate leakage current is increased by about 1 to 1.5 orders of magnitude when the gate voltage is 1.2 V.
FIG. 2 is a circuit diagram showing an inverter chain provided in the receiving circuit. An inverter 101 consisting of a P-channel MOS transistor 101p and an N-channel MOS transistor 101n is connected to an inverter 102 consisting of a P-channel MOS transistor 102p and an N-channel MOS transistor 102n. The P-channel MOS transistors 101p and 102p are connected to a power supply interconnect line, and the N-channel MOS transistors 101n and 102n are connected to a ground interconnect line.
In the thus-structured inverter chain, when a low signal is supplied to a gate of the inverter 101, not only a sub-threshold leakage current but also a gate leakage current as described above flow. The subthreshold leakage current is indicated by a two-dot chain line, and the gate leakage current is indicated by a dashed line. In general, the gate leakage current in the N-channel MOS transistor is greater than that in the P-channel MOS transistor by about 1 to 1.5 orders of magnitude, reflecting the difference between the band structures of the respective MOS transistors.
FIG. 3 is a graph showing the relation of a gate leakage current and a drain current to a gate voltage in the CMOS transistor. In FIG. 3, a solid line shows the gate leakage current of a P-channel MOS transistor, and a dashed line shows the gate leakage current of an N-channel MOS transistor. A one-dot chain line shows the drain current of the P-channel MOS transistor, and a two-dot chain line shows the drain current of the N-channel MOS transistor. FIG. 4 is a band diagram showing the potential relation between a gate electrode and a drain electrode of the N-channel MOS transistor.
In general, the threshold values of the N-channel MOS transistor and the P-channel MOS transistor together consisting of a single CMOS transistor are set to be substantially the same. Therefore, as shown in FIG. 3, when the gate voltage is 0 V, the drain current of the N-channel MOS transistor is equal to that of the P-channel MOS transistor. On the other hand, the gate leakage current in the N-channel MOS transistor is greater than that in the P-channel MOS transistor as described above.
As shown in FIG. 4, a gate-induced drain leakage (GIDL) current also flows. FIG. 5 is a schematic diagram showing a mechanism of a gate-induced drain leakage (GIDL) current. As shown in an arrow A in FIG. 5, the gate-induced drain leakage our (GIDL) occurs in a portion 106 overlapping with-a gate electrode 105 in the cross-sectional view when a power supply potential VDD is supplied to a drain diffusion layer 104 in an N-channel MOS transistor 103.
The object of the present invention is to provide a semiconductor device capable of reducing power consumption while maintaining a desired operation speed thereof.
According to one aspect of the present invention, a semiconductor device comprises a first circuit block to which a power is supplied during an operation thereof and in a stand-by state. The first circuit block comprises a first complementary MOS transistor including a first P-channel MOS transistor and a first N-channel MOS transistor. A gate leakage current of the first N-channel MOS transistor in the stand-by state is set to be substantially equal to a gate leakage current of the first P-channel MOS transistor in the stand-by state.
According to another aspect of the present invention, a semiconductor device comprises a first circuit block, and a second circuit block that operates at a speed higher than that of the first circuit block. The first circuit block comprises a first complementary MOS transistor including a first P-channel MOS transistor and a first N-channel MOS transistor. A gate leakage current of the first N-channel MOS transistor in a stand-by state is set to be substantially equal to a gate leakage current of the first P-channel MOS transistor in the stand-by state.
According to another aspect of the present invention a semiconductor device comprises a first circuit block comprising a first complementary MOS transistor including a first P-channel MOS transistor and a first N-channel MOS transistor, and a second circuit block comprising a second complementary MOS transistor including a second P-channel MOS transistor and a second N-channel MOS transistor. Threshold voltages of the first P-channel MOS transistor and the first N-channel MOS transistor are set to be higher than those of the second P-channel MOS transistor and the second N-channel MOS transistor. A gate leakage current of the first N-channel MOS transistor in a stand-by state is set to be substantially equal to that of the first P-channel MOS transistor.
The thickness of the gate oxide film of the first P-channel MOS transistor is preferably in the range of 20 to 24 xc3x85, and the thickness of the gate oxide film of the first N-channel MOS transistor is preferably in the range of 25 to 29 xc3x85.
According to these aspect of the present invention, since the gate leakage current of the first N-channel MOS transistor in the stand-by state is set to be substantially equal to that of the first P-channel MOS transistor, it is possible to significantly reduce power consumption in the stand-by state, which conventionally has been caused mainly by the gate leakage current of the N-channel MOS transistor. Moreover, since a conventional P-channel MOS transistor may be used as the first P-channel MOS transistor, the driving force thereof is maintained, thereby maintaining the operation speed of a semiconductor device in which theses transistors are provided.
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.